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picture1_Frequency Distribution Ppt 42314 | C262 Slide


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File: Frequency Distribution Ppt 42314 | C262 Slide
motivation early prediction of design characteristics interconnect wirelength done interconnect fanout clock frequency ongoing area etc enable early stage design space exploration abstractions of physically achievable system implementations models to ...

icon picture PPT Filetype Power Point PPT | Posted on 16 Aug 2022 | 3 years ago
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   Motivation
   • Early prediction of design characteristics
        • Interconnect wirelength 
        •                                          Done
          Interconnect fanout
        • Clock frequency
        •                                         Ongoing
          Area, etc.
   • Enable early-stage design space exploration
        • Abstractions of physically achievable system 
          implementations
        • Models to drive efficient system-level optimizations
   • Existing models fail to capture the impact of (1) 
      architectural and (2) implementation parameters
        • Significant deviation against layout data
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (2/12)
   Existing Models
 • Wirelength statistics
      • Christie et al. [2000]
            • Point-to-point wirelength distribution based on Rent’s rule
            • Extends Davis et al. wirelength distribution model
            • Significant deviation against layout data
 • Fanout statistics
      • Zarkesh-Ha et al. [2000]
            • Error in counting the number of m-terminal nets per gate
            • Significant deviation against layout data
 • Existing models fail to take into account combined impacts of 
     architectural and implementation parameters
  Question: What is the impact of considering architectural 
     parameters in early prediction of physical implementation?
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (3/12)
   Implementation Flow and Tools
                           Router / DFT RTL           Architectural
                          (Netmaker / SPIRAL)         Parameters
                              Synthesis
                           (Design Compiler)
  Implementation
    Parameters                                         Wirelength and 
                             Place + Route             Fanout Models
                           (SOC Encounter)
                                                      Model Generation
                            Wiring Reports            (Multiple Adaptive 
                                                     Regression Splines)
  • Timing-driven synthesis, place and route flow
  • Consider both architectural and implementation parameters for 
     more complete modeling of design space
  • Rent parameter extraction through internal RentCon scripts
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (4/12)
   Design of Experiments
  • Netmaker  generation of fully synthesizable router RTL code
  • SPIRAL  generation of fully synthesizable DFT RTL code
  • Libraries: TSMC (1) 130G, (2) 90G, and (3) 65GP
  • Tools: Netmaker (University of Cambridge), SPIRAL (CMU), 
     Synopsys Design Compiler and PrimeTime, Cadence SOC 
     Encounter, Salford MARS 3.0
  • Experimental axes:
      •  Technology nodes: {130nm, 90nm, 65nm}
      •  Clock frequency
      •  Aspect ratio
      •  Row utilization
      •  Architectural parameters: {fw, nvc, nport, lbuf} for routers and 
         {n, width, t, nfifo} for DFT cores
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (5/12)
   Modeling Problem
                                                                             →
   • Accurately predict y given vector of parameters x
                                                     →
   • Difficulties: (1) which variables x to use, and (2) how different 
       variables combine to generate y
                                              →
                                y = f(x)+noise
   • Parametric regression: requires a functional form
   • Nonparametric regression: learns about the best model from 
       the data itself
       For our purpose, allows decoupling of underlying
           architecture / implementation from modeling effort
   • We use nonparametric regression to model interconnect 
       wirelength (WL) and fanout (FO)
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (6/12)
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...Motivation early prediction of design characteristics interconnect wirelength done fanout clock frequency ongoing area etc enable stage space exploration abstractions physically achievable system implementations models to drive efficient level optimizations existing fail capture the impact architectural and implementation parameters significant deviation against layout data ucsd vlsi cad laboratory isocc nov statistics christie et al point distribution based on rent s rule extends davis model zarkesh ha error in counting number m terminal nets per gate take into account combined impacts question what is considering physical flow tools router dft rtl netmaker spiral synthesis compiler place route soc encounter generation wiring reports multiple adaptive regression splines timing driven consider both for more complete modeling parameter extraction through internal rentcon scripts experiments fully synthesizable code libraries tsmc g gp university cambridge cmu synopsys primetime cadence ...

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